1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for correlating error data with defect data.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer composed of a variety of materials may be formed above a wafer. Thereafter, a patterned layer of photoresist may be formed above the process layer using known photolithography techniques. Typically, an etch process is then performed on the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used for a gate electrode structure for transistors. Many times, trench isolation structures are also formed on the substrate of the semiconductor wafer to isolate electrical areas on a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure. Typically, STI structures are formed on the semiconductor wafers by forming trenches in the wafer and filling such trenches with an insulating material, such as silicon dioxide.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed above one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a flowchart depiction of a typical process flow is illustrated. A manufacturing lot of semiconductor wafers 105 are processed (block 210). Upon completion of the processing of the lot of semiconductor wafers 105, defect data is collected for analysis (block 220). The manufacturing control system that performs the semiconductor wafer processing determines the severity of the defects. Based upon the defect data, certain semiconductor wafers 105 and/or the entire lot of semiconductor wafers 105 that have significant defects may be scrapped (block 230). Additionally, electrical testing of the semiconductor wafers 105 may also be performed (block 240). The system also determines the probable amount of errors on the processed semiconductor wafer 105 that may occur based upon results from the electrical testing. As a result, a certain amount of semiconductor wafers 105 may also be scrapped due to the existence of unacceptable electrical faults (block 250).
Problems associated with the current methodology include processing of unnecessary semiconductor wafers 105 due to a lack of predictability of the performance/yield of the semiconductor wafers 105. Often, an entire lot, or a significant number of semiconductor wafers 105 in a lot, may be processed before they are rejected due to defects and/or performance problems detected by electrical testing. Additionally, a lack of predictability as to the yield of a lot of semiconductor wafers 105 may cause an undesirable completion of processing of the lot, which otherwise may have been terminated. Furthermore, manufacturing planning may become difficult due to a lack of a more efficient and accurate prediction of performance and/or yield of processed semiconductor wafers.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for correlating error data with detect data. A semiconductor wafer in a first lot is processed. Defect data based upon analysis of the processed semiconductor wafer is acquired. Electrical test data based upon analysis of the processed semiconductor wafer is acquired. The electrical test data is acquired by performing a wafer electrical testing process on the processed semiconductor wafer. The electrical test data is correlated with the defect data to produce correlated data. At least one of the following is performed: a yield prediction or the performance prediction of a second lot based upon the correlated data. The yield prediction comprises predicting a percentage yield of acceptable semiconductor wafers in the second lot. The performance prediction comprises predicting the performance of the acceptable semiconductor wafers.
In another aspect of the present invention, a system is provided for correlating error data with detect data. The system of the present invention comprises: a process controller adapted to control processing of a lot of semiconductor wafers; a wafer electrical testing unit operatively coupled to the process controller, the wafer electrical testing unit adapted to acquire electrical test data relating to the processed semiconductor wafers; a wafer defect detection unit operatively coupled to the process controller, the wafer detection unit adapted to acquire defect data relating to the processed semiconductor wafers; a defect density model operatively coupled to the wafer defect detection unit, the defect density model adapted to model the defects in the lot; and a yield/performance model operatively coupled to the defect density model, the yield/performance model to quantify at least one of a predicted yield and a predicted performance of semiconductor wafers in the lot.
In yet another aspect of the present invention, a computer readable program storage device encoded with instructions is provided for correlating error data with detect data. The computer readable program storage device encoded with instructions when executed by a computer: processes a semiconductor wafer in a first lot; acquires defect data based upon analysis of the processed semiconductor wafer; acquires electrical test data based upon analysis of the processed semiconductor wafer, electrical test data acquired by performing a wafer electrical testing process on the processed semiconductor wafer; correlates the electrical test data with the defect data to produce correlated data; and performs a yield prediction or a performance prediction of a second lot based upon the correlated data. The yield prediction comprises predicting a percentage yield of acceptable semiconductor wafers in the second lot. The performance prediction comprises predicting the performance of the acceptable semiconductor wafers.